This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-164829, filed on Jun. 5, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates generally to an interpolation circuit having a conversion error correction range for higher-order bits and an A/D conversion circuit utilizing the interpolation circuit, and more particularly to an interpolation circuit that can be realized in a reduced circuit scale, that can be arranged in a multi-stage configuration and that can equalize the common level of the interpolation circuit output, and to an A/D conversion circuit utilizing the interpolation circuit.
2. Description of the Related Art
With the popularization of the digital signal processing technology in recent years, lower power consumption and higher precision have been demanded of A/D conversion circuits that convert analogue signals into digital signals. As an A/D conversion circuit that meets these demands, series-parallel-type A/D conversion circuits utilizing interpolation circuits have been proposed.
FIG. 1 is a circuit diagram illustrating a conventional interpolation-type A/D conversion circuit. This A/D conversion circuit has a reference voltage generation circuit 1 for generating finely divided reference voltages V0 to V8 consisting of voltage dividing elements connected in series between reference power sources VRB and VRT, a differential amplifier array 2 for amplifying respectively the differential voltages between the reference voltages V0 to V8 and an analogue input voltage VIN, switches 3, a higher-order comparator array 4 for comparing differential outputs of each of differential amplifiers and for outputting a positive or a negative output and a higher-order encoder 7 for generating a three (3)-bit digital output by encoding an output of the higher-order comparator 4.
Assuming that the input voltage VIN is positioned between reference voltages V3 and V4, since VIN-V3 greater than 0 and VIN-V4 less than 0, comparators corresponding to the reference voltages respectively outputs a positive output and a negative output so that a higher-order three (3)-bit digital value is detected. That is, where the input voltage VIN is positioned among the reference voltages V0 to V8 is detected by the higher-order comparator array 4 and the result is converted into a three (3)-bit digital value by the encoder 7. A switch in the switches 3 is controlled in response to this higher-order digital value, and the outputs from differential amplifiers connected to the reference voltages V3 and V4 respectively are supplied through switches 3 to a pair of differential amplifiers 5 and 6 in the next stage.
From the differential outputs of the differential amplifiers 5 and 6, a plurality of discrete differential voltages between the differential outputs of the differential amplifiers 5 and 6 are further generated by an interpolation circuit consisting of a voltage dividing element array 8 between the inverted outputs AN and BN of the amplifiers 5 and 6 and a voltage dividing element array 9 between the non-inverted outputs AP and BP of the amplifiers 5 and 6. The discrete differential voltages V13-V17, V23-V27 are supplied respectively to the lower-order comparator arrays 10, 11 and 12. That is, these interpolated differential voltages are input into the lower-order comparator arrays. Then, a lower-order encoder 13 outputs a lower-order two (2)-bit digital value from the outputs of the comparator arrays 10, 11 and 12. A summation circuit 14 sums the higher-order three (3)-bit digital value and the lower-order two (2)-bit digital value and outputs the sum.
FIG. 2 illustrates the principle of the operation of the A/D converter shown in FIG. 1. The axis of abscissas representing the input voltage VIN shows the relation between the input voltage VIN and the reference voltages V0 to V8. The position of the input voltage VIN for the three higher-order bits is detected according to whether the each output (VIN-V1) to (VIN-V7) of the differential amplifier array 2 is positive or negative when the amplification factor of the array 2 is assumed to be 1. In this case, since the analogue input voltage VIN is between the reference voltages V3 and V4, the position of the input voltage VIN can be detected from VIN-V3 greater than 0 (the arrow pointing upward) and VIN-V4 less than 0 (the arrow pointing downward) Furthermore, VIN-V3 and VIN-V4 are supplied respectively to the lower-order differential amplifiers 5 and 6 and are amplified by a factor of m when the amplification factor of the amplifiers 5 and 6 is assumed to be m.
Then, the discrete differential voltages V26-V16, V25-V15 and V24-V14 between those amplified differential voltages (VIN-V3)xc3x97m and (VIN-V4)xc3x97m are generated by the voltage dividing element arrays 8 and 9 and are supplied to the lower-order comparator array 10. Since the border between positive outputs and negative outputs of the comparator array 10 is the level of the input voltage VIN at this moment, two (2) lower-order bits can be detected from the outputs of the comparator array 10.
As apparent from the above description, the interpolation voltages dividing the voltage between the differential outputs of the pair of differential amplifiers 5 and 6 can be generated by the circuit networks of the voltage dividing element arrays 8 and 9. Therefore, these circuit networks can be deemed to be interpolation circuits. Then, those interpolation voltages are compared in the comparator arrays 10, 11 and 12 and a lower-order two (2)-bit digital value can be detected using the result of the comparison. A circuit constituted by adding the comparator array to the interpolation circuit can be deemed to be an A/D conversion circuit. These are the definition of the interpolation circuit and the A/D conversion circuit.
If the outputs of the lower-order comparator arrays 10, 11 and 12 shown in FIG. 1 are all positive or negative even when the input voltage VIN is between the reference voltages V3 and V4, this means that some conversion error has occurred in detecting the three higher-order bits. Then, in an interpolation-type A/D conversion circuit, extrapolation ranges between the reference voltages V2 and V3, and V4 and V5 are provided as conversion ranges for correction in addition to the interpolation range between the reference voltage V3 and V4 in the interpolation circuit, so that, when an error has occurred in a higher-order A/D conversion, the error can be corrected by a lower-order A/D conversion circuit.
Such a proposal is described in, for example, Japanese Patent Application Laid-open (Kokai) No. H04-259372 (published on Sep. 29, 1992) and Japanese Patent Application Laid-open (Kokai) No. H04-303537 (published on Nov. 13, 1992). In the A/D conversion circuit proposed in the former application, four (4) differential amplifiers are added in addition to a pair of differential amplifiers. Then, the outputs of those amplifiers are connected to an interpolation circuit consisting of a circuit network and an extrapolation circuit, and an interpolation differential voltage generated by the interpolation circuit and an extrapolation differential voltage generated by the extrapolation circuit are input into a lower-order comparator. Therefore, three higher-order LSB can be corrected. That is, by generating extrapolation differential voltages outside a range between differential voltages (VIN-V3)xc3x97m and (VIN-V4)xc3x97m in addition to interpolation differential voltages between the differential voltages (VIN-V3)xc3x97m and (VIN-V4)xc3x97m using the two (2) lower-order bits shown in FIG. 2, higher-order bits can be corrected. However, this A/D conversion circuit needs to be added with the differential amplifiers 5,6 and has a problem that the circuit scale becomes large.
On the other hand, in the A/D conversion circuit proposed in the latter application, it is not necessary to add any differential amplifiers. However, by providing a circuit network between the non-inverted output AP and the inverted output AN of one differential amplifier of the pair of differential amplifiers, and between the non-converted output BP and the inverted output BN of the other differential amplifier, an interpolation voltage and an extrapolation voltage are generated. Therefore, dispersion of the common level of those differential voltages is large and the comparators employing these interpolation differential voltages and extrapolation differential voltages as inputs has a problem that it is necessary to design the range of the guaranteed input common level to be wide.
Furthermore, in the conventional examples described above, a multi-stage configurated interpolation circuit or A/D conversion circuit that further detects lower-order bits after detecting two (2) lower-order bits has not yet been proposed.
It is therefore an object of the present invention to provide an interpolation circuit with a reduced circuit scale and an A/D conversion circuit utilizing the same.
Another object of the invention is to provide an interpolation circuit that can be constituted in multiple stages and an A/D conversion circuit utilizing the same.
A further object of the invention is to provide an interpolation circuit that can minimize the variation of the common level of the output of the interpolation circuit and an A/D conversion circuit utilizing the same.
In order to achieve the above objects, according to a first aspect of the present invention, an interpolation circuit for generating interpolation differential voltages and extrapolation differential voltages to a first and a second differential input voltages, comprises a first and a second differential amplifiers for inputting the first and the second differential input voltages, respectively, and for generating a differential output voltage of each amplify respectively between inverted output terminal and non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the non-inverted output terminals of the first and the second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and the second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array.
The interpolation circuit further comprises a third voltage dividing element array disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, so that at least a pair of extrapolation differential voltages are generated from nodes in the third voltage dividing element array. Provision of the third voltage dividing element array enables extrapolation differential voltages to be generated such that the interpolation circuit having a correction range can be realized with a reduced circuit scale. Further, an A/D conversion circuit can be obtained by providing the comparator array for inputting the differential output voltages at this interpolation circuit.
In order to attain the above objects, according to a second aspect of the present invention, a pair of voltage dividing element arrays are disposed respectively between the non-inverted output terminal of the first differential amplifier and the inverted output terminal of the second differential amplifier and between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, in addition to the first and the second voltage dividing element arrays, such that at least a pair of extrapolation differential voltages are generated between the nodes of the pair of voltage dividing element arrays.
Further, in order to attain the above objects, according to a third aspect of the present invention, a pair of voltage dividing element arrays are disposed between the nodes in the first and the second voltage dividing element arrays, in addition to the first and the second voltage dividing element arrays, such that at least a pair of extrapolation differential voltages are generated from the nodes in the pair of voltage dividing element arrays and the nodes in the first or the second voltage dividing element array.
To achieve the above objects, according to a fourth aspect of the present invention, in addition to the first and the second voltage dividing element arrays, a pair of voltage dividing element arrays are disposed between the nodes in the first and the second voltage dividing element arrays, and a third voltage dividing element array (NT3) is disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, such that at least a pair of extrapolation differential voltages are generated from the nodes in the third voltage dividing element array and the outputs of the first and the second differential amplifiers.
To achieve the above objects, according to a fifth aspect of the present invention, in addition to the first and the second voltage dividing element array, a pair of voltage dividing element arrays are disposed between the nodes in the first and the second voltage dividing element arrays. A pair of voltage dividing element arrays are further disposed respectively between the non-inverted output terminal of the first differential amplifier and the inverted output terminal of the second differential amplifier, with another dividing element array being disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, such that at least a pair of extrapolation differential voltages are generated between the nodes in those voltage dividing element arrays.